1. Field of the Invention
The present invention relates to a semiconductor memory having word lines and power source lines such as bit lines.
2. Description of the Prior Art
FIG. 1 is a conventional mask ROM invented by the present inventor. In this mask ROM, a plurality of stripe-like active regions 11 extend parallel to each other in a semiconductor substrate, and a plurality of stripe-like word lines 12 consisting of a conductive film of the first layer on the semiconductor substrate extend parallel to each other and obliquely with respect to the active regions 11.
A plurality of stripe-like power source lines 13 constituted by a conductive film of the second layer on the semiconductor substrate are formed parallel to each other and extend obliquely with respect to the active regions 11. Of the two power source lines 13 adjacent to each other, when one power source line serves as a bit line, i.e., the Vcc line, the other power source line serves as a common line, i.e., the Vss line.
Contact holes 14 are formed at intersections between the active regions 11 and the power source lines 13. In this case, the positional relationship between the active regions 11 and the power source lines 13 is determined so that the contact holes 14 are staggered in the adjacent power source lines 13.
A half of the bit line contact hole 14 and a half of the common line contact hole 14 are present in a unit cell 15. Each contact hole 14 is shared by two unit cells 15 adjacent to each other on the active region 11.
In the mask ROM described above, since the power source lines 13 are not formed by an impurity diffused region in the semiconductor substrate, it is possible to use low-resistance power source lines consisting of a polycide film or the like. Therefore, the mask ROM is suitable for high-speed access.
Since the contact holes 14 are staggered in two adjacent power source lines 13, it is possible to locate the power source lines 13 closer to each other than a structure in which contact holes 14 are adjacent to each other. Therefore, the mask ROM described above is suitable for high integration.
In addition, when an EPROM is formed by the layout shown in FIG. 1, floating gates (not shown) corresponding to two adjacent power source lines 13 are also staggered from each other. Therefore, it is possible to locate the power source lines 13 close to each other. Therefore, this structure is suitable for high integration.
In the layout shown in FIG. 1, although the contact holes 14 are staggered from each other in two adjacent power source lines 13, as described above, the two word lines 12 extending on both sides of each contact hole 14 of one of the power source lines 13 extend on both sides of a corresponding contact hole 14 of the other power source line 13.
For this reason, the word lines 12 and the power source lines 13 inevitably extend obliquely to each other. As a result, whole cell array has a shape of parallelogram. When the cell array of a parallelogram is cut and is bonded to form a rectangular shape for application convenience, peripheral circuits such as a decoder and wiring patterns are undesirably complicated.